使用K8S和QEMU加速软硬件协同仿真 | KC23

Accelerate Software and Hardware Co-Simulation Using K8s and QEMU - Pu Wang, DatenLord

使用K8S和QEMU加速软硬件协同仿真 | Accelerate Software and Hardware Co-Simulation Using K8s and QEMU - Pu Wang, DatenLord

在这个演讲中，我们将展示如何使用K8S和QEMU加速软件和硬件协同仿真。我们的解决方案是完全开源的，将有益于开放硬件社区。首先，我们使用QEMU和Verilator运行协同仿真作业。我们通过利用LibSystemCTLM-SoC（一个赛灵思开源项目）将QEMU和Verilator连接起来，通过套接字或共享内存连接QEMU和仿真器。因此，我们可以在QEMU中运行软件，并与由Verilator模拟的硬件逻辑进行通信。其次，我们通过利用K8S并行运行多个协同仿真作业。我们在一个Pod中部署QEMU和Verilator，然后通过K8S运行Pods，每个Pod都有一个不同的作业，以减少总的协同仿真时间。第三，我们通过将QEMU连接到具有PCIe接口的真实FPGA卡来进一步加速协同仿真。我们扩展了K8S调度器，将FPGA资源分配给协同仿真作业。每个作业将使用（开源的）Xilinx RunTime将特定的硬件逻辑加载到FPGA中。

In this talk, we'll show how to accelerate software and hardware co-simulation using K8S and QEMU. Our solution is fully open source, which will benefit open hardware communities. First, we run a co-simulation job using QEMU and Verilator. We connect QEMU and Verilator by leveraging LibSystemCTLM-SoC (a Xilinx open source project), which connects QEMU with simulators by sockets or shared memory. Thus, we can run software in QEMU and communicate with hardware logic simulated by Verilator. Second, we run multiple co-simulation jobs in parallel by leveraging K8S. We deploy both QEMU and Verilator inside a Pod, and then run the Pods by K8S, each Pod with a different job, so as to reduce the total co-simulation time. Third, we further accelerate co-simulation by connecting QEMU to real FPGA cards with PCIe interface. We extend the K8S scheduler to allocate FPGA resources to co-simulation jobs. Each job will load specific hardware logic into an FPGA using (open source) Xilinx RunTime.

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